1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a so-called BiCMOS semiconductor integrated circuit device fabricated by forming both a bipolar transistor and a MOS transistor on a semiconductor substrate.
2. Description of the Related Art
FIGS. 1 to 5 are sectional views showing the steps of a method of fabricating a conventional BiCMOS integrated circuit in order. First, as shown in FIG. 1, n.sup.+ -type regions 2 in p-type substrate are formed in portions below a buried collector region of a bipolar transistor and an n-type well region of a MOS transistor. Generally, these regions are formed by solid-phase diffusion of As and Sb. A mask pattern of a resist film 4 is formed, and p-type regions 3 are selectively formed by ion implantation in portions below an isolation region of the bipolar transistor and a p-type well region of the MOS transistor.
In FIG. 2, epitaxial growth is performed to form an n-type epitaxial layer 5 with a low impurity concentration. In FIG. 3, an n-type region (n-type well region) 7 is formed in the epitaxial layer 5 above the n.sup.+ -type region 2 in the MOS transistor region. To decrease the collector resistance, a deep n-type region 8 reaching the buried collector region is formed. P-type regions 6 are formed in the epitaxial layer 5 above the p-type regions 3. These regions 6 form a p-type well region in the MOS transistor region and electrically isolate the bipolar transistor in the isolation region.
In FIG. 4, an oxide film 91 is formed by LOCOS (Local Oxidation of Silicon) to perform element isolation. An impurity is selectively doped into a portion serving as a channel of the MOS transistor by ion implantation, and the impurity profile is so controlled as to obtain a desired threshold. A gate oxide film 92 and gate electrodes 11 are formed. N-type impurity regions 12 are selectively formed by ion implantation in regions serving as the source and the drain of an n-channel MOS transistor and in a region serving as the collector contact of the bipolar transistor. Analogously, p-type impurity regions 13 are selectively formed by ion implantation in regions serving as the source and the drain of a p-channel MOS transistor and in a region serving as the base contact of the bipolar transistor. A low-doped shallow p-type impurity region 14 is formed as a base region on the surface of the epitaxial layer 5 above the buried collector of the bipolar transistor by using ion implantation.
In FIG. 5, an oxide film 93 is formed as a first insulating interlayer on the entire surface of the device. This oxide film 93 is selectively removed only from an emitter formation region of the bipolar transistor to thereby form a contact hole. A first interconnecting line 16 is formed by using polysilicon. An n-type impurity is doped into the polysilicon by using ion implantation and activated by some appropriate heating step. At the same time, the impurity in the polysilicon is diffused by solid phase into the emitter formation region of the bipolar transistor through the contact hole, thereby forming an n-type impurity region (emitter) 15. As (arsenic) is generally used as this impurity.
An oxide film 94 is formed as a second insulating interlayer on the entire surface of the device. The first and the second insulating interlayers (93 and 94) are removed only from contact regions, and second interconnecting lines 17 are formed in these regions by using a conductive material. Although an oxide film 95 covering the interconnecting lines 17 is finally formed in FIG. 5, third and fourth insulating interlayers and third and fourth interconnecting lines are subsequently formed where necessary. After all these interconnecting lines are formed, the surface is covered with an SiN film as a protective film to complete the device.
The characteristic features of the above device are as follows. Since the n-type epitaxial layer 5 with a low impurity concentration is sandwiched between the p-type impurity region 14 as the base region and the n.sup.+ -type region 2 as the collector region, the junction capacitance between the base and the collector can be decreased. This is important for a high-speed operation of the bipolar transistor. Also, since the buried layer 2 or 3 with a high impurity concentration is formed below the well region of the MOS transistor, the impurity concentration of the well can be decreased while a good latch-up resistance is maintained. Consequently, the junction capacitance between the source drain and the well of the MOS transistor can be decreased.
In the fabrication method as described above, the growth temperature of the epitaxial layer 5 is as high as 1000.degree. C. or higher. Accordingly, the impurity in the highly doped buried layer 2 or 3 diffuses in the direction of film thickness of the epitaxial layer 5 (FIG. 2). If the film thickness of the epitaxial layer 5 is small, therefore, the profile near the channel of the MOS transistor may vary. This is particularly a problem in the n-channel MOS transistor because the p-type region 3 using boron (B) with a high diffusing capability influences the p-type well region.
The above phenomenon will be described in detail below by using mathematical expressions. When the diffusion of the impurity from the buried layer is taken into consideration, the concentration distribution of the impurity in the epitaxial layer can be expressed as follows (equation (1)). The second term of this equation indicates the diffusion of the impurity from the buried layer. ##EQU1## C.sub.T(x) : the total impurity concentration in the epitaxial layer. C.sub.1 : the impurity concentration of the heavily doped impurity layers of the first and second conductivity types.
D.sub.1 : the diffusion coefficient of the impurities in the heavily doped impurity layers of the first and second conductivity types at the temperature of epitaxial growth. PA1 D.sub.EPI : the diffusion coefficient of the impurity doped into the epitaxial layer at the temperature of epitaxial growth. PA1 N.sub.EPI : the initial concentration of the impurity doped into the epitaxial layer. PA1 t: the time required for epitaxial growth. PA1 v: the epitaxial growth velocity. PA1 erf !: an error function. PA1 erfc !: a complementary error function. PA1 T: the thickness (=vt) of the epitaxial layer. PA1 x: the depth from the surface of the epitaxial layer. PA1 .phi..sub.F : the Fermi potential. PA1 Q.sub.BD : the total amount of the impurities present within the depletion layer (near the channel). PA1 V.sub.th : the threshold voltage of the MOS transistor. PA1 .DELTA.Q.sub.BD : the total change amount of the impurities within the depletion layer near the channel caused by the diffusion of the impurities from the first and the second heavily doped impurity layers. PA1 .DELTA.V.sub.th : the change amount of V.sub.th caused by the change in the impurity concentration near the channel. PA1 .sup..epsilon. S: the dielectric constant of silicon. PA1 V.sub.bi : the diffusion potential. PA1 N.sub.EPI : the impurity concentration in the epitaxial layer. PA1 N.sub.B : the impurity concentration in the base region. PA1 V.sub.BC : the voltage between the base and the collector. PA1 V.sub.CC : the power supply voltage. PA1 .mu..sub.n : the electron mobility in silicon. PA1 C.sub.(x) : the concentration of the impurities, diffused from the heavily doped impurity layers of the first and the second conductivity types, in the epitaxial layer of the second conductivity type. PA1 x.sub.1 : the depth in the substrate at which the concentration of the impurities, diffused from the heavily doped impurity layers of the first and the second conductivity types, in the epitaxial layer of the second conductivity type is equal to the impurity concentration in the epitaxial layer. PA1 x.sub.B : the junction depth in the base region. PA1 x.sub.nmax : the maximum width of the depletion layer extending toward the collector. PA1 C.sub.1 : the impurity concentration in the heavily doped impurity layers of the first and the second conductivity types. PA1 D.sub.1 : the diffusion coefficient of the impurities in the heavily doped impurity layers of the first and the second conductivity types at the temperature of epitaxial growth. PA1 t: the time required for epitaxial growth. PA1 erf !: an error function. PA1 T: the thickness of the epitaxial layer. PA1 x: the depth from the surface of the epitaxial layer. PA1 f.sub.T : the cutoff frequency PA1 .tau..sub.EC : the signal transmission time between the emitter and the collector. PA1 .tau..sub.E : the charging time of the emitter depletion layer. PA1 .tau..sub.B : the base transit time or the base charging time. PA1 .tau..sub.X : the transit time of the collector depletion layer. PA1 .tau..sub.C : the collector charging time. PA1 R.sub.C : the collector resistance.
By using the above equation, the concentration of only the impurity diffused from the buried layer can be expressed as follows (equation (2)). ##EQU2## C.sub.(x) : the concentration of the impurities, diffused from the heavily doped impurity layers of the first and second conductivity types, in the epitaxial layer of the second conductivity type.
The impurity concentration on the surface of the epitaxial layer, i.e., near the channel of the MOS transistor changes due to the impurity diffusion from the buried layer, and as a consequence the threshold of the MOS transistor varies. FIG. 6 shows the way the impurity in the buried layer 2 or 3 with a high impurity concentration diffuses in the direction of film thickness of the epitaxial layer 5. The threshold of the MOS transistor is expressed as follows. ##EQU3## C.sub.OX : the gate capacitance. V.sub.FB : the flat band voltage.
Accordingly, the change in the threshold due to the diffusion of the impurities from the buried layers is expressed as follows. ##EQU4## x.sub.dmax : the maximum width of the depletion layer of the MOS transistor.
It is evident from equations (2), (3), (4), and (5) that when the film thickness T of the epitaxial layer 5 is small, the effects of becoming C(x) in the neighborhood of channel larger are that .DELTA.Q.sub.BD increases and largely changes the threshold voltage. A threshold variation like this is undesirable in respect of device design and hence must be minimized. For example, to decrease the threshold variation caused by the above phenomenon to 10% or less of the initial threshold, it is necessary to set the film thickness T of the epitaxial layer so that equation (6) below holds. ##EQU5##
To solve this problem, the epitaxial layer 5 must be grown to have a large enough film thickness (e.g., 1.2 .mu.m or larger). However, if this film thickness is applied to the epitaxial layer 5 of the bipolar transistor, the width of the n-type lightly doped region of the lightly doped collector region of the epitaxial layer 5 between the base and the collector regions increases to be larger than the width necessary to decrease the junction capacitance. Since, the lightly doped collector region of an excess high-resistance epitaxial layer exists, the collector resistance of the bipolar transistor is increased, and this hinders a high-speed operation in the high injection region.
The above problem can also be considered as follows by using mathematical expressions. FIG. 7 shows the concentration profile of the bipolar transistor in the direction of depth of the substrate. The collector in a portion in contact with the base is the epitaxial layer 5 with a low concentration. Equation (7) expresses the junction capacitance between the base and the collector. Equation (7) shows that the junction capacitance can be decreased when the impurity concentration in the epitaxial layer is low. ##EQU6## C.sub.J : the junction capacitance between the base and the collector. q: the elementary charge.
Equation (8) below expresses the width of the depletion layer between the base and the collector. When the impurity concentration in the epitaxial layer is low, the depletion layer widens. Equation (8) shows that this decreases the junction capacitance between the base and the collector. ##EQU7## W: the width of the depletion layer between the base and the collector.
In an actual operating range, however, V.sub.BC is not higher than power supply voltage V.sub.CC (V.sub.BC .ltoreq.V.sub.CC), and so the width of the depletion layer has an upper limit indicated by equation (9) below. ##EQU8## W.sub.max : the maximum width of the depletion layer between the base and the collector.
If, therefore, the film thickness T of the epitaxial layer is too large and the depth of the lightly doped collector region of the epitaxial layer is larger than the maximum width of the depletion layer, a high-resistance epitaxial layer region X as shown in FIG. 7 exists. Accordingly, the collector resistance increases as indicated by equations (10), (11), and (12) below. ##EQU9## .DELTA.R.sub.C : the increase in the collector resistance due to the existence of the epitaxial layer region.
Equations (13), (14), and (15) below indicate a cutoff frequency f.sub.T of the bipolar transistor. It can be understood from these equations that an increase in the collector resistance caused by too large a film thickness of the epitaxial layer decreases f.sub.T. ##EQU10## EQU .tau..sub.EC =.tau..sub.E +.tau..sub.B +.tau..sub.X +.tau..sub.C( 14) EQU .tau..sub.C =R.sub.C C.sub.J ( 15)
To prevent the increase of the collector resistance, it is only necessary to decrease the film thickness of the epitaxial layer so that no the lightly doped collector region of high-resistance epitaxial layer exists. However, as illustrated in FIG. 8, the depletion layer does not extend to x.sub.nmax any longer if an upper end x.sub.1 of the highly doped buried layer region is positioned above the maximum depletion layer extending toward the collector. That is, when EQU x.sub.B +x.sub.nmax &gt;x.sub.1 ( 16)
holds, a maximum depletion layer width W.sub.max ' is decreased as follows (equation (17)). EQU W.sub.max -W.sub.max '=x.sub.nmax -(x.sub.1 -x.sub.B)&gt;0 (17)
If this is the case, although the collector resistance does not increase, the collector capacitance increases as indicated by equation (18) below, and this decreases f.sub.T. ##EQU11## C.sub.J ': the junction capacitance between the base and the collector when the extension of the depletion layer is restricted.
To improve the performance of the bipolar transistor, therefore, it is necessary to optimize the film thickness T of the epitaxial layer as indicated by equation (19) below. EQU x.sub.1 =x.sub.B +x.sub.nmax ( 19)
Since, however, the optimum film thickness indicated by the above equation is usually smaller than the necessary film thickness of the MOS transistor, it is difficult to optimize the two film thicknesses at the same time.
This problem does not arise if the buried layers, i.e., the n-type region 2 and the p-type region 3 are not formed below the MOS transistor. However, realizing a retrograde structure without forming any buried layer requires high energy ion implantation. This degrades the characteristics of a MOS transistor due to defects occurring in an epitaxial layer during the high energy ion implantation. Also, if no retrograde structure is used, it is necessary to increase the impurity concentration in a well in order to ensure a high latch-up resistance. Consequently, the junction capacitance between the source drain and the well cannot be decreased, and this is an obstacle to a high-speed operation of the MOS transistor.
It is possible to decrease the thickness of the epitaxial layer 5 by deeply forming the p-type impurity region 14 as the base region of the bipolar transistor. However, it is also important to minimize the thickness of the base in order to achieve high performance of the bipolar transistor. Therefore, this countermeasure leading to an increase of the base thickness cannot be performed.
In addition, the temperature of epitaxial growth can be lowered to control the diffusion of the buried regions 2 and 3. However, if the temperature is lowered, the quality of the epitaxial layer degrades or the productivity decreases due to the low growth rate. Alternatively, the impurity concentrations in the buried regions 2 and 3 can be decreased. However, if the impurity concentrations in these regions 2 and 3 are decreased, the collector resistance rises and this increases the series resistance of the bipolar transistor.
In the MOS transistor, it is also possible to cancel variations in the profile caused by the diffusion of the buried regions 2 and 3 by well increasing the channel ion implantation amount. However, this increases the junction capacitance between the source drain and the well, or the large ion implantation amount deepens (raises) the threshold of the MOS transistor. These influences are disadvantageous to a low-voltage operation and a high-speed operation.